1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a metal wiring in a semiconductor device, which can improve the reliability of multilayered metal wiring.
2. Background of the Related Art
As the packing density of semiconductor devices becomes higher, there have been many investigations into multilayered metal wiring. Multilayered metal wiring facilitates simple wiring design, setting of a wiring resistance, and selection of current capacity and the like in reserve. As a material for the multilayered wiring, aluminum and alloys of aluminum are widely used; these materials possess good electric conductivity and are low cost. Additionally, a plug layer of tungsten having a good contact resistance is employed primarily for bringing an upper wiring and a lower wiring into contact as the packing density of semiconductor devices increases.
A related art multilayered metal wiring will be explained with reference to the attached drawings. FIG. 1 illustrates a section of a related art multilayered metal wiring in a semiconductor device, and FIGS. 2A-2L illustrate sections showing the steps of a related art method for forming multilayered metal wiring in a semiconductor device.
A structure of the related art multilayered metal wiring in a semiconductor device will be explained. The related art multilayered metal wiring in a semiconductor device is provided with a first interlayer insulating film 22 having a contact hole formed on a semiconductor substrate 21, an adhesive/barrier layer 24 at the bottom and sides of the contact hole excluding an upper portion of the contact hole, a tungsten plug layer 26 formed in the contact hole excluding the upper portion of the contact hole, an adhesive layer 27 formed on the tungsten plug layer 26 in the upper portion of the contact hole and a first wiring layer 29 formed on the interlayer insulating film 22. A portion of first wiring layer 29 fills the upper portion of the contact hole on the adhesive layer 27 with a depression at a center.
A second interlayer insulating film 30 having a via hole exposes a portion of the first wiring layer 29 formed on the first interlayer insulating film 22 and an adhesive/barrier layer 31 is formed on a bottom surface (an upper surface of the first wiring layer) and side surfaces of the via hole excluding an upper portion of the via hole. A tungsten plug layer 33 fills the via hole excluding the upper portion of the via hole, and a second wiring layer 34 in contact with the tungsten plug layer 33 formed on the second interlayer insulating film 30 inclusive of the upper portion of the via hole with a depression at a center thereof. Centers of the first and second wiring layers 29 and 34 are depressed because there are tungsten recesses formed when the underlying tungsten plug layers 26 and 33 are formed.
The steps of a related art method for forming multilayered metal wiring in a semiconductor device having the aforementioned structure will be explained.
Referring to FIG. 2A, a first interlayer insulating film 22 is formed on an entire surface of a semiconductor substrate 21 having cell transistors (not shown) and the like formed thereon. As shown in FIG. 2B, the first interlayer insulating film 22 is etched selectively, to form a contact hole 23, which exposes a surface of the semiconductor substrate 21, selectively. Then, as shown in FIG. 2C, an adhesive/barrier layer 24 is formed on an entire surface inclusive of the contact hole 23. The adhesive layer is formed for enhancing an adhesive force between the material layer for forming the plug, and the substrate and the contact hole in a following process for forming the plug while the barrier layer is formed for use as a diffusion barrier. Then, as shown in FIG. 2D, a tungsten film 25 is formed by CVD (Chemical Vapor Deposition), to fill the contact hole 23, completely.
As shown in FIG. 2E, the tungsten film 25 is etched back until an upper surface of the first interlayer insulating film 22 inclusive of the contact hole 23 is exposed, to form a tungsten plug layer 26. In this instance, the tungsten layer in the contact hole 23 is recessed. Then, as shown in FIG. 2F, an adhesive layer 27 is formed for enhancing an adhesive force. Then, as shown in FIG. 2G, a material layer 28 for forming wiring is formed on the adhesive layer 27. As shown in FIG. 2H, the material layer 28 for forming wiring and the adhesive layer 27 are etched selectively by photolithography to form a first wiring layer 29.
Subsequently, as shown in FIG. 2I, a second interlayer insulating film 30 is formed on the first wiring layer 29 and the first interlayer insulating film 22. As shown in FIG. 2J, the second interlayer insulating film 30 is removed selectively, to form a via hole to expose the first wiring layer 29. An adhesive/barrier layer 31 is formed on an entire surface of the second interlayer insulating film 30 inclusive of the via hole, and a tungsten film 32 is deposited by CVD on an entire surface. Then, as shown in FIG. 2K, the tungsten film 32 is etched back to expose an upper surface of the second interlayer insulating film 30, to form a tungsten plug layer 33. In this instance too, the tungsten layer in the via hole is depressed. As shown in FIG. 2L, a material layer for forming wiring is formed on an entire surface inclusive of the tungsten plug layer 33 and etched selectively, to form a second wiring layer 34. Such a method of forming a wiring by stacking via holes is a method for forming a wiring that is useful as device packing density increases, a process generally used in a logic circuit using multilayered wiring having more than 4 layers.
However, the etch back process in formation of the tungsten plug layer in such a stacked via structure is not conducive to actual mass production, because the CMP (Chemical Mechanical Polishing) used in the mass production has a high cost. Nevertheless, the etch back process can not be used because a section of the metal wiring in contact with the plug layer can not maintain a rectangular form due to the depression formed in the plug layer when the plug layer is formed by etch back.
The related art multilayered metal wiring in a semiconductor device has the following problems. The depression formed in the tungsten layer in the contact/via hole region during formation of a tungsten plug layer impedes formation of metal wiring with a rectangular cross-section. This feature impedes formation of a via hole for forming an upper wiring in a subsequent process, and leads to creation of unstable forms of the barrier layer and the plug layer which are deposited after the formation of the via hole. Such a structure causes partial increase of a current density in operation of the device, deteriorating a device reliability and yield. Thus, in formation of multilayered wiring of a stacked via type, the formation of plug layer by etch back can not be applied to actual mass production due to the foregoing problems.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Accordingly, the present invention is directed to a method for forming a metal wiring in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a metal wiring in a semiconductor device, which can improve a reliability of multilayered metal wiring and simplify the forming process.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for forming a metal wiring in a semiconductor device includes the steps of (1) forming a first insulating film on a semiconductor substrate, (2) etching the first insulating film to form a first contact hole, (3) forming a first plug in the first contact hole, and removing a portion of the first insulating film for planarizing the first plug and the first insulating film, (4) forming a first wiring layer on a portion of the first insulating film on and around the first plug, (5) forming a second insulating film on the first wiring layer and the first insulating film, (6) etching the second insulating film for forming a second contact hole which exposes the first wiring layer, (7) forming a second plug in the second contact hole and removing a portion of the second insulating film, for planarizing the second plug and the second insulating film, and (8) forming a second wiring layer on the second plug.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.